Logic Synthesis and Verification Algorithms

Verilog Digital System Design: Register Transfer Level Synthesis, Testbench,...

Verilog Digital System Design : Register Transfer Level Synthesis

Algorithmic and Register-Transfer Level Synthesis: The System Architects Workben

Verilog Digital System Design: Register Transfer Level Synthesis, Testbench,...

Algorithmic and Register-Transfer Level Synthesis: The System Architect S Wor-,

Algorithmic and Register-Transfer Level Synthesis: The System... - 9781461288152