Logic Design and Verification Using SystemVerilog (Revised)

Logic Design and Verification Using SystemVerilog (Revised) by Donald Thomas

Logic Design and Verification Using Syst... Paperback – March 1, 2016 Paperback

Logic Design And Verification Using Systemverilog (Revised)

Finite State Machines in Hardware: Theory and Design (w. VHDL and SystemVerilog)

Logic Design and Verification Using Systemverilog, Paperback by Thomas, Donal...

SystemVerilog for Verification: A Guide - Hardcover, by Spear Chris - Acceptable