Publisher Description

This book shows that digitally assisted analog to digital converters are not the only way to cope with poor analog performance caused by technology scaling. It describes various analog design techniques that enhance the area and power efficiency without employing any type of digital calibration circuitry. These techniques consist of self-biasing for PVT enhancement, inverter-based design for improved speed/power ratio, gain-of-two obtained by voltage sum instead of charge redistribution, and current-mode reference shifting instead of voltage reference shifting. Together, these techniques allow enhancing the area and power efficiency of the main building blocks of a multiplying digital-to-analog converter (MDAC) based stage, namely, the flash quantizer, the amplifier, and the switched capacitor network of the MDAC. Complementing the theoretical analyses of the various techniques, a power efficient operational transconductance amplifier is implemented and experimentally characterized. Furthermore, a medium-low resolution reference-free high-speed time-interleaved pipeline ADC employing all mentioned design techniques and circuits is presented, implemented and experimentally characterized. This ADC is said to be reference-free because it precludes any reference voltage, therefore saving power and area, as reference circuits are not necessary. Experimental results demonstrate the potential of the techniques which enabled the implementation of area and power efficient circuits.

Notes

Describes various design techniques to enhance the power and area efficiency of building blocks for multiplying digital-to-analog converter (MDAC) based ADCs, such as Pipeline, Algorithmic, and multi-step Flash 
Enables analog designers to enhance the performance of a range of circuits, without employing any type of digital assistance (calibration) 
Includes complete design flow of an ADC based on the proposed circuits and design techniques

Back Cover

This book shows that digitally assisted analog-to-digital converters are not the only way to cope with poor analog performance caused by technology scaling. It describes various analog design techniques that enhance the area and power efficiency without employing any type of digital calibration circuitry. These techniques consist of self-biasing for PVT enhancement, inverter-based design for improved speed/power ratio, gain-of-two obtained by voltage sum instead of charge redistribution, and current-mode reference shifting instead of voltage reference shifting. Together, these techniques allow enhancing the area and power efficiency of the main building blocks of a multiplying digital-to-analog converter (MDAC) based stage, namely, the flash quantizer, the amplifier, and the switched capacitor network of the MDAC. Complementing the theoretical analyses of the various techniques, a power efficient operational transconductance amplifier is implemented and experimentally characterized. Furthermore, a medium-low resolution reference-free high-speed time-interleaved pipeline ADC employing all mentioned design techniques and circuits is presented, implemented and experimentally characterized. This ADC is said to be reference-free because it precludes any reference voltage, therefore saving power and area, as reference circuits are not necessary. Experimental results demonstrate the potential of the techniques which enabled the implementation of area and power efficient circuits. Describes various design techniques to enhance the power and area efficiency of building blocks for multiplying digital-to-analog converter (MDAC) based ADCs, such as Pipeline, Algorithmic, and multi-step Flash; Enables analog designers to enhance the performance of a range of circuits, without employing any type of digital assistance (calibration); Includes complete design flow of an ADC based on the proposed circuits and design techniques.

Table of Contents

Introduction.- General Overview of Pipeline Analog-to-Digital Converters.- Capacitor Mismatch-Insensitive Multiplying-DAC Topologies with Unity Feedback Factor.- Application of Circuit Enhancement Techniques to ADC Building Blocks.- Design of a 7-bit 1GS/s CMOS Two-Way Interleaved Pipeline ADC.- Integrated Prototypes and Experimental Results.- Conclusions.

Feature

Describes various design techniques to enhance the power and area efficiency of building blocks for multiplying digital-to-analog converter (MDAC) based ADCs, such as Pipeline, Algorithmic, and multi-step Flash Enables analog designers to enhance the performance of a range of circuits, without employing any type of digital assistance (calibration) Includes complete design flow of an ADC based on the proposed circuits and design techniques

Details