SystemVerilog For Design: A Guide to Using SystemVerilog for Hardware Design...

Systemverilog for Design by Stuart Sutherland

SystemVerilog for Design : A Guide to Using SystemVerilog for Har

SystemVerilog For Design by Stuart Sutherland, Simon Davidmann, Peter Flake

Finite State Machines in Hardware: Theory and Design (w. VHDL and SystemVerilog)

SystemVerilog for Verification: by Spear, Chris, Tumbush, Greg

SVA: The Power of Assertions in SystemVerilog - 9783319071381

Writing Testbenches using SystemVerilog