Using Vlsi to Reduce Serialization and Memory Traffic in Shared Memory Parallel

Using Vlsi to Reduce Serialization and Memory Traf

Designing Vlsi Network Nodes to Reduce Memory Traffic in a Shared Memory

CMOS VLSI Design : A Circuits and Systems Perspective

Performance of Shared Memory in a Parallel Computer (Classic Reprint)

Tlb Consistency on Highly-Parallel Shared-Memory Multiprocessors

Basic VLSI Design (Silicon Systems Engineering) Textbook by PUCKNELL AND ESHRAGH

Efficient Synchronization on Multiprocessors With Shared Memory