Using Vlsi to Reduce Serialization and Memory Traffic in Shared Memory Parallel

Using Vlsi to Reduce Serialization and Memory Traf

Digital Signal Processing in VLSI R J Higgins

Designing Vlsi Network Nodes to Reduce Memory Traffic in a Shared Memory

Digital Integrated Circuits Rabaey 1996 VLSI Design Engineering Prentice Hall

Designing Vlsi Network Nodes to Reduce Memory Traffic in a Shared Memory

Vlsi Circuit Layout: Theory and Design (IEEE Press) By Te Chiang Hu & Ernest S.

Using OpenMP: Portable Shared Memory Parallel Programming (Scientific and En...